A multi-port semiconductor memory device uses a plurality of ports for individually accessing a plurality of memory cells therein. In a multi-port semiconductor memory device, at least two ports may be simultaneously used to access one memory cell, during a read operation and a write operation. Such simultaneous access can cause an address contention. When the address contention is caused in the multi-port semiconductor memory device, interference between the at least two ports may occur. As a result, operations of the multi-port semiconductor memory device may fail because the interference may cause data errors. For example, when a first port is used for a read operation and a second port is used for a write operation, the read operation on the first port may cause errors during the write operation on the second port.